Embodiments of the present invention relate to a semiconductor memory device, and more specifically to a cell structure of a phase change memory (PCM) device, which includes a plurality of vertically laminated unit cells.
Generally, a non-volatile memory device (e.g., a magnetic memory device, a phase change memory (PCM) device, or the like) has a data processing speed similar to that of a volatile random access memory (RAM) device. The non-volatile memory device also preserves data even when power is turned off.
FIGS. 1A and 1B illustrate a conventional phase change resistor (PCR) element 4.
Referring to FIGS. 1A and 1B, the PCR element 4 includes a top electrode 1, a bottom electrode 3, and a phase change material (PCM) layer 2 located between the top electrode 1 and the bottom electrode 3. If a voltage and a current are applied to the top electrode 1 and the bottom electrode 3, a current signal is provided to the PCM layer 2, and a high temperature is induced in the PCM layer 2. As a result, the electrical conductivity of the PCM layer 2 changes depending on resistance variation. The PCM layer 2 may be formed of AgInSbTe. The PCM layer 2 uses chalcogenide, the main components of which are chalcogen elements such as S, Se and Te. The PCM layer 2 may be formed of germanium antimony tellurium (Ge2Sb2Te5) composed of Ge—Sb—Te.
FIGS. 2A and 2B illustrate a phase change principle of the conventional PCR element 4.
Referring to FIG. 2A, if a low current smaller than a threshold value flows in the PCR element 4, the PCM layer 2 has a temperature suitable for a crystalline phase. Therefore, the PCM layer 2 changes to the crystalline phase, such that it is changed to a low-resistance phase material.
On the other hand, as shown in FIG. 2B, if a high current greater than the threshold value flows in the PCR element 4, the PCM layer 2 has a temperature higher than a melting point. Therefore, the PCM layer 2 changes to an amorphous phase, such that it is changed to a high-resistance phase material.
As described above, the PCR element 4 can store data corresponding to two resistance phases. For example, if the PCR element 4 has a low-resistance phase set to data ‘1’ and the PCR element 4 has a high-resistance phase set to data ‘0’, the PCR element 4 may store two logic states of data.
In addition, since a phase of the PCM layer (i.e., a phase change resistive material) 2 is not changed even when a phase change memory device is powered off, the aforementioned data can be stored as non-volatile data.
FIG. 3 illustrates a write operation of a conventional PCR element.
Referring to FIG. 3, when a current flows between the top electrode 1 and the bottom electrode 3 of the PCR element 4 for a predetermined time, heat is generated. Therefore, the PCM layer 2 is changed from a crystalline phase to an amorphous phase in response to heat applied to the top electrode 1 and the bottom electrode 3.
In this case, assuming that a low current smaller than a threshold value flows in the PCR element 4 for a predetermined time, the PCM layer 2 with a crystalline phase is formed by a low-temperature heating state, such that the PCR element 4 becomes a low-resistance element having a set state. Otherwise, assuming that a high current greater than the threshold value flows in the PCR element 4 for a predetermined time, the PCM layer 2 with an amorphous phase is formed by high-temperature heating, such that the PCR element 4 becomes a high-resistance element having a reset status. Thus, a difference between two phases is represented by a variation in electrical resistance.
Accordingly, in order to write the set state during a write operation mode, a low voltage is applied to the PCR element 4 for a long period of time. On the other hand, in order to write the reset state during the write operation mode, a high voltage is applied to the PCR element 4 for a short period of time.
However, a problem of phase change memory (PCM) devices using the PCR element is an excessively high write current for writing data in a cell. Therefore, the number of cells where data is simultaneously written is limited, such that write performance is deteriorated.